The field of the present invention pertains to the testing of integrated circuits using automated testing equipment (ATE). More specifically, the invention pertains to circuits that enhance the functionality of test data pattern designs used in ATE and provides the capability to perform variable modulo looping of vector data sequences out of memory where the vector data rate is higher than the data rate of the memory being used.
Computer systems and electronic devices are continually growing in capability and complexity. The size and complexity of integrated electronic systems are likewise increasing, making it critical that the component parts of these systems operate without fault. This requires that each component, or integrated circuit xe2x80x9cchip,xe2x80x9d be rigorously tested before it is sold. However, as integrated circuit chips become more powerful, the methods and systems required to detect flaws within them become increasingly sophisticated and expensive.
Integrated circuit designs have become more complex in part because they are made more dense. As a result, they have become progressively harder to test in order to ensure correct and complete functionality. Higher densities are achieved in part by reducing the amount of space between transistors and other components which comprise the integrated circuit. As such, the xe2x80x9cplace and routexe2x80x9d tolerances for the integrated circuit are reduced, and the potential for introducing fabrication errors and introducing structural faults in the circuit increases. Additionally, the complicated placement of the internal structure and nature of the defects encountered in such high density integrated circuits requires the use of sophisticated algorithms in order to ensure adequate defect detection, e.g., being able to determine whether structural defects between the closely spaced gate elements, such as a bit short, broken link, or the like, exist. Hence, the testing cost can be very significant for the latest and largest high density integrated circuits (ICs).
Very sophisticated programs, called automatic test pattern generation (ATPG) programs, are used to analyze the integrated circuit designs and generate therefrom test patterns (e.g., also referred to as test programs or test vectors) used for testing the devices in automatic test equipment (ATE) systems. The objective of the ATPG program is to generate accurate, high defect coverage test patterns as efficiently as possible, to reduce the cost. As a result of analyzing the target design, the ATPG tool determines a stimulus for all the accessible points of the target design.
During chip verification, this stimulus is applied by the tester to the integrated circuit and the real time response of the chip is compared with the pre-computed response of the test pattern. ATE systems are required to provide a contiguous flow of digital data that is used to generate the input signals required to stimulate the IC under test, plus provide the expected response data that is compared to the output data generated by the IC. This data is referred to as xe2x80x9ctest pattern dataxe2x80x9d. If the IC""s output data is different from the provided expect data, then the IC fails the test and is classified as defective.
As discussed above, testing systems, or xe2x80x9ctestersxe2x80x9d are used to apply test vectors to a device under test, and compare the resultant data generated by the device under test to expected data. Typically, the more pins available on a tester, the more expensive the tester equipment. For example, today testers cost approximately $2,000-$10,000 per pin supported. There is a high demand for technology and related services that can reduce the costs of these very expensive testers.
Test pattern data is structured as a sequence of multi-bit words referred to as xe2x80x9cvectors.xe2x80x9d The number of data bits contained within a single vector is the number of IC signal pins times the number of bits implemented for each tester pin (e.g., typically 1-3). These vectors are required to be provided to the IC at a specific programmed rate (termed the test rate xe2x80x9cperiodxe2x80x9d) which is determined by the IC""s specified operating rate against which it is being tested.
The test pattern data is normally stored in the tester""s solid state memory which can consist of static RAM (SRAM), synchronous dynamic RAM (SDRAM), or a combination of the two. The amount of test pattern data required by the vast majority of ICs are of significant enough volume to where SDRAMs are the only economical and feasible alternative.
FIG. 1 illustrates a conventional communication configuration 10 using an SDRAM 12 for pattern storage and a coupled xe2x80x9cFirst-In-First-Outxe2x80x9d (FIFO) memory 16. While SDRAMs have an acceptable high average bandwidth, they require periodic interruptions to the data flow for internal data refreshing and for row address changes. In order to sustain a constant flow of data to the IC under test, a memory (FIFO) is often used as a buffer. The buffer 16 is used to convert the non-constant data rate flow 14 to supply a constant data rate flow 18 that is based on the average bandwidth of the data from the SDRAM 12.
FIG. 2A illustrates a communication configuration 20 used in cases when the required data rate out of the FIFO 16 (FIG. 1) is higher than the average bandwidth of the SDRAM-to-FIFO interface 14 (FIG. 1). In these cases, the data width of the SDRAM can be increased. As shown in FIG. 2A, the input port 22 of the FIFO memory is made wider than its output port 24, which contains a 4-to-1 multiplexer. Generally the required vector rate is higher than the maximum data transfer rate of the memory being used. To provide higher vector rates, the memory can be organized with multiple vectors stored at each memory location. In the case shown in FIG. 2A, the SDRAM supplies four vectors on each clock cycle.
FIG. 2B illustrates the resulting timing diagrams 34 of the configuration shown in FIG. 2A. In this example, four vectors are stored at each location. Assuming the maximum memory transfer rate is 100 MHz (signal 26) from the SDRAM, then the maximum vector rate would be 400 Mhz (signal 30) supplied by the FIFO. Within one clock cycle 26, the SDRAM supplies four vectors 28 in parallel, and the FIFO then supplies these four individual vectors in series fashion 32 thereby quadrupling the vector rate.
This conventional method suffices for providing an uninterrupted flow of test pattern data from the SDRAM to the IC signals pins as long as the data pattern retrieved from the SDRAM is contiguous. However, there are often requirements that a sequence of particular vector locations in memory be repeated over a number of times. The number of times for any particular sequence may either be pre-determined, or be conditional, e.g., require the situation where the loop repeats until a specified condition is achieved. These sequences are called xe2x80x9cvector routinesxe2x80x9d or xe2x80x9cvector loops.xe2x80x9d
FIG. 3A illustrates an example of this type of sequence 40 or xe2x80x9cvector loop.xe2x80x9d In the test vectors applied 40, the vector sequence 44, comprising vectors 4-7, is repeated three times. Further, the vector sequence 48, comprising vectors 11-13, is repeated two times.
As shown in FIG. 3B, a further potential requirement of the looping capability is the ability to xe2x80x9cnestxe2x80x9d vector loops within the sequence 50. Here, the vector sequence 52, comprising vectors 4-7, is repeated three times. However, a nested loop 58 includes vectors 9-16. In sequence 58 are two sequences 54 and 56. Sequence 54 is repeated twice and sequence 56 is repeated twice each time sequence 58 is performed. Therefore, sequence 58, and its nested loops 54 and 56, are repeated twice. The looping capability generally infers that the entire sequence of data being looped-on must be re-accessed for each iteration of the loop. In the conventional systems, to provide this capability there have been two general implementations, each with a unique set of restraints and considerations.
FIG. 4A illustrates the first conventional art implementation 60 that utilizes a higher speed secondary memory 64, typically an SRAM, to pre-store all occurrences of any pattern sequence that is to be looped-on. This secondary memory 64 is much smaller and more expensive than the main SDRAM memory. The function actually implemented by this approach is generally a xe2x80x9csubroutinexe2x80x9d capability, whereas all re-executable subroutines of data are pre-stored in this secondary memory. This implementation also expands the main vector memory data 62 to include additional control/address bits which are used to select and activate a particular section of the secondary memory. The control instructions, xe2x80x9ccall,xe2x80x9d invoke subroutines located in the SRAM memory 64 which return to the SDRAM 62 by the xe2x80x9creturnxe2x80x9d commands. This secondary xe2x80x9csubroutinexe2x80x9d memory may, or may not, also have the ability to loop on data sequences within its own memory space, as depicted in FIG. 4A, by the xe2x80x9cloopxe2x80x9d commands.
There are two major restrictions imposed with the implementation of FIG. 4A. The first is that the amount of memory allocated for subroutines is limited by the size of the higher speed, but smaller sized SRAM, constraining both the number of available subroutines and the maximum size of the subroutines. The SRAM is limited to a small size namely because: (1) it is very expensive; and (2) it is very technically difficult and complex to fabricate large SRAMs. A second restriction occurs when the implementation fetches multiple vectors per memory access in order to achieve higher vector rates. In this case, the xe2x80x9ccallingxe2x80x9d vector may only be able to branch to the subroutine on a modulo vector boundary (e.g., word boundary) based on the number of vectors contained per memory location (e.g., limited to every 4th vector). If the secondary memory also utilizes multiple vectors per memory access, that would impose a limitation that each subroutine would have to contain an even modulo number of vectors.
A second conventional implementation utilizes a single large memory that may or may not also employ multiple vectors per memory for higher data rates. If SDRAM is used with the FIFO implementation described earlier, looping would involve reloading the FIFO in advance of the loop execution, which would be prohibited if the loop was to be terminated by a non-deterministic real-time condition. This is the case because by the time the real-time condition was determined, the FIFO would need to have been loaded with speculative information that was a result of a xe2x80x9cguessxe2x80x9d at the outcome of the condition. If incorrectly predicted, the speculative information would have to be cleared out, thereby breaking the continuous data flow. Also, the modulo loop boundary constraints imposed by multiple vectors per memory location would still exist with this second conventional implementation.
FIG. 4B illustrates a table 70 regarding another requirement that prior art test implementations may not adequately address. Namely, a contiguous flow of data is required between the end of one pattern sequence to the start of a next pattern sequence that is stored at an arbitrary SDRAM address. If multiple vectors are stored at each SDRAM address location, then the pattern sequence size must always be a modulo of the number of vectors at each location according to the prior art. An example of this problem is depicted in FIG. 4B. Pattern xe2x80x9cAxe2x80x9d initially consists of 67 vectors. After the completion of the last vector in Pattern xe2x80x9cA,xe2x80x9d Pattern xe2x80x9cBxe2x80x9d is to be initiated with no interruptions in the vector data flow. To correct this problem, an extra xe2x80x9cdummy vectorxe2x80x9d may be inserted at the end of Pattern xe2x80x9cAxe2x80x9d to satisfy the modulo boundary requirement. However, this is often an undesirable solution.
Accordingly, what is needed is an ATE system that solves the above recited problems. More specifically, what is needed is an ATE system that allows high speed application of test patterns while allowing nested looping without restrictions to loop size or modularity, e.g., that does not have modulo loop constraints. What is further needed is an ATE system that can loop and/or branch from any vector in a multiple vector accessed word to any vector in another multiple vector accessed word without incurring any time displacement. What is also needed, is such an ATE system that supplies vector data at a high but constant data rate and that efficiently uses SRAM resources. What is also needed is an ATE system that can continue from any vector in a multiple vector accessed word to the first vector in another pattern stored in memory (at an arbitrary location) without incurring any time displacement. The embodiments of the present invention provide such advantages. These and other aspects of the present invention not recited above will become clear within the descriptions of the present invention presented below.
What is described is an SRAM efficient ATE system that can perform high speed nested loops without constraints on loop size or modularity and that can loop and/or branch from any vector in a multiple vector accessed word to any vector in another multiple vector accessed word without incurring any time displacement. In one embodiment, the maximum required vector rate is less than or equal the average sustained data rate of the SDRAM and is less than or equal to the maximum access rate of the dual port SRAM""s memory B. In this embodiment, the output of the SDRAM""s memory A consists of one control word and one vector (nV=1). The input/output port widths of the SRAM""s memory B are the same. An SRAM cache memory is used to store n number of control words following a start of loop flag and similarly, an SRAM cache memory is used to store n number of vectors following the start of loop flag. At the end of the loop flag, if the condition exists not to loop, then data continues to be taken from SRAM memory B. If looping is to occur, then n data is taken from the cache memories until the new SDRAM address has been accessed and resultant data written into SRAM memory B, a duration at least shorter then the time required to supply the n data from the cache.
In another embodiment, the maximum required vector rate is greater than the average sustained data rate of the SDRAM""s memory A, but is equal to or less than the maximum access rate of the SRAM""s memory B. In this embodiment, the output of the SDRAM""s memory A consists of multiple control words and vectors. The input port of the SRAM""s memory B is some multiple of the output port width. This embodiment also provides the caching abilities described above.
In another embodiment, the maximum required vector rate is greater than both the average sustained data rate of the SDRAM""s memory A and the maximum access rate of the SRAM""s memory B. In this embodiment, the output of the SDRAM""s memory A consists of one or more control words (nW) and (nWxc3x97nV) number of vectors. The input port of the SRAM""s memory B is nW times the width of the output port. The output port of Memory B contains 2 or more vectors per word. This embodiment also provides the caching abilities described above and further operates on multiple vectors at a time without any modulo loop restrictions.
In another embodiment, one vector sequence may call another vector sequence and the vector data may include an xe2x80x9cend of patternxe2x80x9d control code which indicates the end of the presently addressed pattern. Unlike other control codes, this code is detected at the output of memory A and prior to writing the word into memory B. Detection of this code causes the memory address control unit to suspend writing into memory B, re-access the location of the next pattern to be executed from memory A and commence loading the start of that pattern into memory E (a special FIFO memory). The xe2x80x9cend of patternxe2x80x9d word also specifies the xe2x80x9clast vector in patternxe2x80x9d value, e.g., (0xe2x88x92(nVxe2x88x921)). When the last vector in the existing pattern is executed, multiplexer B commences reading the initial sequence of the next pattern from memory E via a multiplexer G. Multiplexer G is set to the proper selection code based on the value of the multiplexer C selection in use at the time of the last word execution and the xe2x80x9clast vector in patternxe2x80x9d value. In this way, the memories and the multiplexers dynamically select the correct vector from multi-vector words to facilitate contiguous data flow with no interruptions or restrictions on vector placement.
More specifically, an embodiment of the present invention includes an automated test equipment (ATE) system comprising: a first memory for storing a vector loop comprising: test vectors; a loop begin indicator; and loop end indicator, a buffer memory coupled to the first memory to receive data at a variable rate and for supplying buffered data at a constant rate; control logic for decoding indicators within the buffered data; address logic, responsive to the control logic, for re-addressing the first memory upon detection of the loop end indicator provided the vector loop is to be re-addressed; a second memory for storing n vectors following the loop begin indicator and for supplying the n vectors upon detection of the loop end indicator provided the vector loop is to be re-addressed; and a first multiplexer for supplying data to a device under test at a constant rate, the first multiplexer for selecting vector data from the second memory while the first memory is being re-addressed and for selecting vector data from the buffer memory after the first memory has been re-addressed.
Another embodiment includes an automated test equipment (ATE) system comprising: a first memory for storing a vector loop comprising: vectors; a loop begin indicator; and loop end indicator; a buffer memory operable to receive data at a variable rate from the first memory and for supplying words at a constant rate, each word comprising nV vectors; control logic for decoding indicators within the words supplied by the buffer memory; address logic, responsive to the control logic, for re-addressing the first memory upon detection of the loop end indicator provided the vector loop is to be re-addressed; a second memory for storing n vector words following the loop begin indicator and for supplying the n vector words upon detection of the loop end indicator provided the vector loop is to be re-addressed; and a multiplexer pipeline operable to select vectors from among two vector words simultaneously, the multiplexer pipeline coupled to receive vector words originating from the second memory while the first memory is being re-addressed and coupled to receive vector words originating from the buffer after the first memory has been re-addressed, the multiplexer pipeline for supplying vectors at a constant rate.
Another embodiment includes an automated test equipment (ATE) system comprising: a first memory for storing a first vector sequence and a second vector sequence, the first vector sequence comprising a pattern end indicator; a first buffer operable to receive data of the first vector sequence at a variable rate from the first memory and for supplying words at a constant rate, each word comprising nV vectors; a second buffer operable to receive data of the second vector sequence at a variable rate from the first memory and for supplying words at a constant rate, each word comprising nV vectors; pattern detect logic for detecting the pattern end indicator at an output of the first memory; address logic, responsive to the pattern detect logic, for re-addressing the first memory upon detection of the pattern end indicator to a start address of the second vector sequence to load the second buffer with the start of the second vector sequence; and a multiplexer pipeline operable to select vectors from among two vector words simultaneously, the multiplexer pipeline for selecting between vector words originating from the first buffer and vector words originating from the second buffer and for supplying vectors at a constant data rate.